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october 2008 rev 1 1/36 1 L6756D 2/3/4 phase buck controller for vr10, vr11 and vr11.1 processor applications features ltb technology ? enhances load transient response 2 to 4 scalable phase operation dual-edge asynchronous architecture psi# input with programmable strategy imon output flexible driver support 7/8 bit programmable output - vr10/11.1 dac 0.5% output voltage accuracy full-differential curr ent sense across dcr integrated remote sense buffer feedback disconnection protection adjustable oscillator from 100 khz to 1 mhz lsless startup to manage pre-biased output programmable soft-start threshold sensitive enable pin for vtt sensing vfqfpn40 6x6 mm package applications high-current vrm / vrd for desktop / server / workstation cpus graphic cards low-voltage, high-current power supplies high-density dc / dc converters description L6756D is a two-to-four phase controller designed to power intel?s most demanding processors and, most in general, low-voltage, high-current power supplies. the device features ltb technology ? to provide the fastest response to load transients thus minimizing the output filter composition. L6756D embeds selectable dac: output voltage is programmable up to 1.6000 v (intel vr10 and vr11.x dacs) managing dvid transitions with 0.5% output voltage accuracy over line, load and temperature variations. the device assures fast protection against load over current and under / over voltage. feedback disconnection prevents from damaging the load in case of misconnections in the system board. low-side-less start-up allows soft-start over pre- biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. L6756D is available in vfqfpn 6x6 mm package vfqfpn40 6x6 mm table 1. device summary order code package packing L6756D vfqfpn40 tube L6756D tr vfqfpn40 tape and reel www.st.com www..net
contents L6756D 2/36 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 output voltage load-line definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 output voltage offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 dynamic vid transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6.1 lsless start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 output voltage monitoring an d protections . . . . . . . . . . . . . . . . . . . . . 26 6.1 overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 vr_rdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 low power-state management and psi# . . . . . . . . . . . . . . . . . . . . . . . . 28 8 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
L6756D contents 3/36 9 system control loop com pensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 ltb technology ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . 34 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
typical application circuit and block diagram L6756D 4/36 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical 4phase application circuit "//4 5'!4% 0(!3% ,'!4% (3 ,3 6 ). , # (& # "5,+?). # $%# '.$ 07- 6## , "//4 5'!4% 0(!3% ,'!4% (3 ,3 , # (& # $%# '.$ 07- 6## , "//4 5'!4% 0(!3% ,'!4% (3 ,3 , # (& # $%# '.$ 07- 6## , "//4 5'!4% 0(!3% ,'!4% (3 ,3 , # (& # $%# '.$ 07- 6## , ' ' ' ' $26/. #3 #3. #3 #3. #3 #3. #3 #3. , ). 6$20 6&" #/-0 ),)- 2/3# '.$ 6## 34,$ # & 2 & 2 &" 2 /3# 2 ' 2 ' 2 ' 2 ' 2 # 2 # 2 # 2 # %. #05 # /54 # -,## %. 06)$bus)nterfacingwith#05 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 03)62 2 ),)- 2 33 33 2 ,4"?'!). ,4"?'!). # ( # ) 2 ) # ,4 " 2 ,4 " 63%. &"' ,4 " 62%& '.$ 03)?!6)$?3%, )-/. 62?2$9 %. %. %. !-v
L6756D typical application circuit and block diagram 5/36 figure 2. typical 3phase application circuit %227 8*$7( 3+$6( /*$7( +6 /6 9 ,1 / & +) & %8/.b,1 & '(& *1' 3:0 9&& / %227 8*$7( 3+$6( /*$7( +6 /6 / & +) & '(& *1' 3:0 9&& / %227 8*$7( 3+$6( /*$7( +6 /6 / & +) & '(& *1' 3:0 9&& / * * * * '5921 &6 &61 &6 &61 &6 &61 &6 &61 / ,1 9'53 9)% &203 ,/,0 526& *1' 9&& 67/' & ) 5 ) 5 )% 5 26& 5 * 5 * 5 * 5 * 5 & 5 & 5 & &38 & 287 & 0/&& (1 39,'exv,qwhuidflqjzlwk&38 9,' 9,' 9,' 9,' 9,' 9,' 9,' 9,' 36,95 5 ,/,0 5 66 66 5 /7%b*$,1 /7%b*$,1 & + & , 5 , & /7% 5 /7% 96(1 )%* /7% 95() *1' 36,b$9,'b6(/ ,021 95b5'< (1 (1 (1 !-v
typical application circuit and block diagram L6756D 6/36 figure 3. typical 2phase application circuit "//4 5'!4% 0(!3% ,'!4% (3 ,3 6 ). , # (& # "5,+?). # $%# '.$ 07- 6## , "//4 5'!4% 0(!3% ,'!4% (3 ,3 , # (& # $%# '.$ 07- 6## , ' ' ' ' $26/. #3 #3. #3 #3. #3 #3. #3 #3. , ). 6$20 6&" #/-0 ),)- 2/3# '.$ 6## 34,$ # & 2 & 2 &" 2 /3# 2 ' 2 ' 2 ' 2 ' 2 # 2 # #05 # /54 # -,## %. 06)$bus)nterfacingwith#05 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 03)62 2 ),)- 2 33 33 2 ,4"?'!). ,4"?'!). # ( # ) 2 ) # ,4 " 2 ,4 " 63%. &"' ,4 " 62%& '.$ 03)?!6)$?3%, )-/. 62?2$9 %. %. !-v
L6756D typical application circuit and block diagram 7/36 1.2 block diagram figure 4. block diagram to0(!3% /3#),,! 4/2 /3# #522%.4 "!,!.#% #3 %. 62?2$ 9 2eference #/-0 63%. &"' %22/2 !-0,)&)%2 6&" #3. #3 ) $2//0 k k k k 2%-/4% "5&&%2 &5,,9$)&&%2%.4)!, #522%.43%.3% /540546/,4!'% -/.)4/2!.$ 02 /4%#4)/.-!.!'%-%.4 3 3 3 3 #3. #3 #3. #3 #3. ' ' ' ' 4/4#522%.4 2eference ,$ $!##/.42/,,/')# 6)$ 6$20 #3 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 03)62 62%& ,4"?"//34 ,4"4echnology #/.42/,$%4%#4/2 ,4"?"//34 ,4"'!). ,4 " 63%. ) $2//0 ),)- 6## '.$ 6## 2/3# /3# 33 63%. $26/. 03)?! ) -/. )-/. 6max#,!-0 !-v
pins description and connection diagrams L6756D 8/36 2 pins description and connection diagrams figure 5. pins connection (top view) 2.1 pin descriptions %. 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 03)62 33 2/3# ),)- !'.$ ,4 " &"' 63%. #/-0 6&" 6$20 )-/. 03)?! ,4"'!). 62?2$9 6## $'.$ 62%& ' ' ' ' $26/. #3 #3. #3 #3. #3 #3. #3 #3. ,$ !-v table 2. pin description pin# name function 1en vr enable. internally pulled-up by 10 a to 3.3 v. pull-low to disable the device, set free or pull up above turn-on threshold to enable the controller. 2 to 9 vid0 to vid7 voltage identification pins. 3.3 v compatible, they allow programming output voltage as specified in ta b l e 6 and ta bl e 7 according to vr10/1 pin status. 10 psi# / vr10 according to the status of psi_a, the functionality of this pin changes as below: psi# : power state indicator input. connect to the psi# pin on the cpu to manage low-power state. when asserted (pulled low), the controller will act as programmed on the psi_a pin. vr10 : it allows selecting between vr10 (short to sgnd, see ta b l e 6 ) or vr11 (floating, see ta b l e 7 ) dacs. 11 ss by connecting a resistor r ss to gnd, it allows programming the soft-start time. soft-start time t ss will proportionally change with a gain of 18.52 [s / k ]. connect 27 k resistor to program t2 = 500 s. the same slope implemented to reach v boot has to be considered also when the reference moves from v boot to the programmed vid code. the pin is kept to a fixed 1.24 v.
L6756D pins description and connection diagrams 9/36 12 rosc oscillator pin. it allows programming the switching frequency f sw of each channel: the equivalent switching frequency at the load side results in being multiplied by the phase number n. frequency is programmed according to t he resistor connected from the pin to gnd or vcc with a gain of 10 khz/a. leaving the pin floating programs a switching frequency of 200 khz per phase. 13 ilim over current set pin. connect to gnd through a r ilim resistor to set the oc threshold. this pin sources a copy of the droop current; oc is set when the voltage at the pin crosses 1.7 v (typ). see section 6.4 for details. 14 gnd all the internal references are referred to this pin. connect to the pcb signal ground. 15 ltb load transient boost technology ? input pin. see section 9.2 for details. 16 fbg remote ground sense. connect to the negative side of the load to perform remote sense. 17 vsen output voltage monitor, manages ovp and uvp protections. connect to the positive side of the load to perform remote sense. a fixed 50 a current is sunk through this pin to implement small positive offset for the regulated voltage. see section 5.4 for details. 18 comp error amplifier output. connect with an r f - c f // c h to vfb. the device cannot be disabled by pulling low this pin. 19 vfb error amplifier inverting input. connect with a resistor r fb to vsen and with an r f - c f // c h to comp. 20 vdrp a current proportional to the total cu rrent read is sourced from this pin according to the current reading gain. short to vfb to implement voltage positioning or connect to gnd through a resistor and filter with 1 nf capacitor to implement an additional load indicator. 21 cs1n channel 1 current sense negative input. connect through a rg resistor to the output-side of the channel inductor. 22 cs1 channel 1 current sense positive input. connect through an r-c filter to the phase-side of the channel 1 inductor. 23 cs2n channel 2 current sense negative input. connect through a rg resistor to the output-side of the channel inductor. w hen working at 2 phase, still connect through rg to cs2 and then to the regulated voltage. 24 cs2 channel 2 current sense positive input. connect through an r-c filter to the phase-side of the channel 2 inductor. when working at 2 phase, short to the regulated voltage. 25 cs3n channel 3 current sense negative input. connect through a rg resistor to the output-side of the channel inductor. 26 cs3 channel 3 current sense positive input. connect through an r-c filter to the phase-side of the channel 3 inductor. 27 cs4n channel 4 current sense negative input. connect through a rg resistor to the output-side of the channel inductor. when working at 2 or 3 phase, still connect through rg to cs3 and then to the regulated voltage. table 2. pin description (continued) pin# name function
pins description and connection diagrams L6756D 10/36 28 cs4 channel 4 current sense positive input. connect through an r-c filter to the phase-side of the channel 4 inductor. when working at 2 or 3 phase, short to the regulated voltage. 29 drvon external driver enable. cmos output used to control the external driver status: pulled-low to manage hiz conditions or pulled-high for normal driver switching. 30 to 33 g1 to g4 pwm outputs. connect to external drivers pwm inputs. the device is able to manage hiz status by setting the pins floating. by shorting to gnd g4 or g2 and g4, it is possible to program the device to work at 3 or 2 phase respectively. 34 vref this pin provide a 2.5 v reference. filter with 1 nf (max) to sgnd. 35 gnd all the internal references are referred to this pin. connect to the pcb signal ground. 36 vcc device power supply. operative voltage is 12 v 15 %. filter with at least 1 f mlcc vs. ground. 37 vr_rdy open drain output set free after ss has finished and pulled low when triggering any protection. pull up to a voltage lower t han 3.3 v (typ), if not used it can be left floating. 38 ltb_gain load transient boost technology ? gain pin. see section 9.2 for details. 39 psi_a psi action configuration pin. this pins configures the functionalit y of the psi# / vr10 pin according to ta b l e 9 as follow: vr10: short to sgnd to configure the vi d_sel functionality. the controller will not manage low power-states but will be backward compatible with vr10 / vr11 platforms. psi#: the device will work in vr11 mode and perform low power-states management through the psi# pin. see section 7 for details. 40 imon current monitor output. a current proport ional to the read current is sourced from this pin. connect through a resistor r mon to fbg to implement a load indicator. connect the load indicator directly to vr11.1 cpus.the pin voltage is clamped to 1.1v max to preserve the cpu from excessive voltages. thermal pad thermal pad connects the silicon substrate and makes good thermal contact with the pcb. connect to the pgnd plane. table 2. pin description (continued) pin# name function
L6756D pins description and connection diagrams 11/36 2.2 thermal data table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 35 c/w r thjc thermal resistance j unction to case 1 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c
electrical specifications L6756D 12/36 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings 3.2 electrical characteristics symbol parameter value unit v cc to pgnd 15 v all other pins to pgndx -0.3 to 3.6 v table 5. electrical characteristics (v cc = 12 v 15 %, t j = 0 c to 70 c unless otherwise specified) symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current 25 ma uvlo vcc vcc turn-on vcc rising 9.75 v vcc turn-off vcc falling 7 v oscillator, soft-start and enable f sw main oscillator accuracy 185 200 215 khz oscillator adjustability r osc = 33 k 500 khz v osc pwm ramp amplitude 1.5 v fault voltage at pin osc ov, uv latch active 3 3.6 v soft- start t d1 - initial delay 1 2 3 ms t d2 - r ss = 27 k 400 500 600 s t d3 - v boot 100 200 300 s boot voltage - v boot 1.026 1.081 1.136 v en v en rising 0.80 0.85 0.90 v hysteresis 100 mv reference and dac k vid v out accuracy vsen to v core ; fbg to gnd core -0.5 0.5 % i os offset vsen = 0.5000 v to 1.6000 v -40 -50 -60 a a 0 ea dc gain 130 db sr slew rate comp to sgnd = 10 pf 25 v/ s vid il vid threshold, input low 0.3 v vid ih input high 0.8 v
L6756D electrical specifications 13/36 psi#/vr10 input threshold input low 0.3 v input high 0.8 v vref reference voltage 2.450 2.500 2.550 v ltbgain ltbgain voltage 1.24 v differential current sense and current monitor k idroop droop accuracy rg = 1 k ; i droop < 100 a-4 4 a k imon imon accuracy rg = 1 k ; i mon < 100 a-6 6 a k ilim ilim accuracy rg = 1 k ; i ilim < 100 a-8 8 a pwm outputs gx output high i = 1 ma 3 v output low i = -1 ma 0.2 v i gx test current 10 a drvon output low i = -5 ma 0.4 v protections ovp vsen rising; wrt ref. 150 175 200 mv uvp under voltage protection vsen fal ling; wrt ref; ref > 500mv -400 mv vr_rdy voltage low i vr_rdy = -4 ma 0.4 v v fb-disc fb disconnection v csn rising, above vsen 550 650 750 mv fbg disc fbg disconnection ea ni input wrt vid 400 500 600 mv v ilim_oc oc threshold v ilim rising 1.6 1.7 1.8 v v ilim rising, during dvid 2.5 v table 5. electrical characteristics (continued) (v cc = 12 v 15 %, t j = 0 c to 70 c unless otherwise specified) symbol parameter test conditions min. typ. max. unit
electrical specifications L6756D 14/36 table 6. voltage identification (vid) for intel vr11.x mode hex code vid[7:0] output voltage hex code vid[7:0] output voltage hex code vid[7:0] output voltage hex code vid[7:0] output voltage 0 0 off 4 0 1.21250 8 0 0.81250 c 0 0.41250 0 1 off 4 1 1.20625 8 1 0.80625 c 1 0.40625 0 2 1.60000 4 2 1.20000 8 2 0.80000 c 2 0.40000 0 3 1.59375 4 3 1.19375 8 3 0.79375 c 3 0.39375 0 4 1.58750 4 4 1.18750 8 4 0.78750 c 4 0.38750 0 5 1.58125 4 5 1.18125 8 5 0.78125 c 5 0.38125 0 6 1.57500 4 6 1.17500 8 6 0.77500 c 6 0.37500 0 7 1.56875 4 7 1.16875 8 7 0.76875 c 7 0.36875 0 8 1.56250 4 8 1.16250 8 8 0.76250 c 8 0.36250 0 9 1.55625 4 9 1.15625 8 9 0.75625 c 9 0.35625 0 a 1.55000 4 a 1.15000 8 a 0.75000 c a 0.35000 0 b 1.54375 4 b 1.14375 8 b 0.74375 c b 0.34375 0 c 1.53750 4 c 1.13750 8 c 0.73750 c c 0.33750 0 d 1.53125 4 d 1.13125 8 d 0.73125 c d 0.33125 0 e 1.52500 4 e 1.12500 8 e 0.72500 c e 0.32500 0 f 1.51875 4 f 1.11875 8 f 0.71875 c f 0.31875 1 0 1.51250 5 0 1.11250 9 0 0.71250 d 0 0.31250 1 1 1.50625 5 1 1.10625 9 1 0.70625 d 1 0.30625 1 2 1.50000 5 2 1.10000 9 2 0.70000 d 2 0.30000 1 3 1.49375 5 3 1.09375 9 3 0.69375 d 3 0.29375 1 4 1.48750 5 4 1.08750 9 4 0.68750 d 4 0.28750 1 5 1.48125 5 5 1.08125 9 5 0.68125 d 5 0.28125 1 6 1.47500 5 6 1.07500 9 6 0.67500 d 6 0.27500 1 7 1.46875 5 7 1.06875 9 7 0.66875 d 7 0.26875 1 8 1.46250 5 8 1.06250 9 8 0.66250 d 8 0.26250 1 9 1.45625 5 9 1.05625 9 9 0.65625 d 9 0.25625 1 a 1.45000 5 a 1.05000 9 a 0.65000 d a 0.25000 1 b 1.44375 5 b 1.04375 9 b 0.64375 d b 0.24375 1 c 1.43750 5 c 1.03750 9 c 0.63750 d c 0.23750 1 d 1.43125 5 d 1.03125 9 d 0.63125 d d 0.23125 1 e 1.42500 5 e 1.02500 9 e 0.62500 d e 0.22500 1 f 1.41875 5 f 1.01875 9 f 0.61875 d f 0.21875 2 0 1.41250 6 0 1.01250 a 0 0.61250 e 0 0.21250 2 1 1.40625 6 1 1.00625 a 1 0.60625 e 1 0.20625
L6756D electrical specifications 15/36 2 2 1.40000 6 2 1.00000 a 2 0.60000 e 2 0.20000 2 3 1.39375 6 3 0.99375 a 3 0.59375 e 3 0.19375 2 4 1.38750 6 4 0.98750 a 4 0.58750 e 4 0.18750 2 5 1.38125 6 5 0.98125 a 5 0.58125 e 5 0.18125 2 6 1.37500 6 6 0.97500 a 6 0.57500 e 6 0.17500 2 7 1.36875 6 7 0.96875 a 7 0.56875 e 7 0.16875 2 8 1.36250 6 8 0.96250 a 8 0.56250 e 8 0.16250 2 9 1.35625 6 9 0.95625 a 9 0.55625 e 9 0.15625 2 a 1.35000 6 a 0.95000 a a 0.55000 e a 0.15000 2 b 1.34375 6 b 0.94375 a b 0.54375 e b 0.14375 2 c 1.33750 6 c 0.93750 a c 0.53750 e c 0.13750 2 d 1.33125 6 d 0.93125 a d 0.53125 e d 0.13125 2 e 1.32500 6 e 0.92500 a e 0.52500 e e 0.12500 2 f 1.31875 6 f 0.91875 a f 0.51875 e f 0.11875 3 0 1.31250 7 0 0.91250 b 0 0.51250 f 0 0.11250 3 1 1.30625 7 1 0.90625 b 1 0.50625 f 1 0.10625 3 2 1.30000 7 2 0.90000 b 2 0.50000 f 2 0.10000 3 3 1.29375 7 3 0.89375 b 3 0.49375 f 3 0.09375 3 4 1.28750 7 4 0.88750 b 4 0.48750 f 4 0.08750 3 5 1.28125 7 5 0.88125 b 5 0.48125 f 5 0.08125 3 6 1.27500 7 6 0.87500 b 6 0.47500 f 6 0.07500 3 7 1.26875 7 7 0.86875 b 7 0.46875 f 7 0.06875 3 8 1.26250 7 8 0.86250 b 8 0.46250 f 8 0.06250 3 9 1.25625 7 9 0.85625 b 9 0.45625 f 9 0.05625 3 a 1.25000 7 a 0.85000 b a 0.45000 f a 0.05000 3 b 1.24375 7 b 0.84375 b b 0.44375 f b 0.04375 3 c 1.23750 7 c 0.83750 b c 0.43750 f c 0.03750 3 d 1.23125 7 d 0.83125 b d 0.43125 f d 0.03125 3 e 1.22500 7 e 0.82500 b e 0.42500 f e off 3 f 1.21875 7 f 0.81875 b f 0.41875 f f off table 6. voltage identification (vid) for intel vr11.x mode (continued) hex code vid[7:0] output voltage hex code vid[7:0] output voltage hex code vid[7:0] output voltage hex code vid[7:0] output voltage
electrical specifications L6756D 16/36 table 7. voltage identifications (vid) for intel vr10 mode + 6.25 mv vid4 vid3 vid2 vid1 vid0 vid5 vid6 output voltage vid4 vid3 vid2 vid1 vid0 vid5 vid6 output voltage 01010111. 60000 11010111.2 0000 01010101. 59375 11010101.1 9375 01011011. 58750 11011011.1 8750 01011001. 58125 11011001.1 8125 01011111. 57500 11011111.1 7500 01011101. 56875 11011101.1 6875 01100011. 56250 11100011.1 6250 01100001. 55625 11100001.1 5625 01100111. 55000 11100111.1 5000 01100101. 54375 11100101.1 4375 01101011. 53750 11101011.1 3750 01101001. 53125 11101001.1 3125 01101111. 52500 11101111.1 2500 01101101. 51875 11101101.1 1875 01110011. 51250 11110011.1 1250 01110001. 50625 11110001.1 0625 01110111. 50000 11110111.1 0000 01110101. 49375 11110101.0 9375 01111011. 48750 1111101 off 01111001. 48125 1111100 off 01111111. 47500 1111111 off 01111101. 46875 1111110 off 10000011. 46250 00000011.0 8750 10000001. 45625 00000001.0 8125 10000111. 45000 00000111.0 7500 10000101. 44375 00000101.0 6875 10001011. 43750 00001011.0 6250 10001001. 43125 00001001.0 5625 10001111. 42500 00001111.0 5000 10001101. 41875 00001101.0 4375 10010011. 41250 00010011.0 3750 10010001. 40625 00010001.0 3125 10010111. 40000 00010111.0 2500 10010101. 39375 00010101.0 1875
L6756D electrical specifications 17/36 10011011. 38750 00011011.0 1250 10011001. 38125 00011001.0 0625 10011111. 37500 00011111.0 0000 10011101. 36875 00011100.9 9375 10100011. 36250 00100010.9 8750 10100001. 35625 00100000.9 8125 10100111. 35000 00100110.9 7500 10100101. 34375 00100100.9 6875 10101011. 33750 00101010.9 6250 10101001. 33125 00101000.9 5625 10101111. 32500 00101110.9 5000 10101101. 31875 00101100.9 4375 10110011. 31250 00110010.9 3750 10110001. 30625 00110000.9 3125 10110111. 30000 00110110.9 2500 10110101. 29375 00110100.9 1875 10111011. 28750 00111010.9 1250 10111001. 28125 00111000.9 0625 10111111. 27500 00111110.9 0000 10111101. 26875 00111100.8 9375 11000011. 26250 01000010.8 8750 11000001. 25625 01000000.8 8125 11000111. 25000 01000110.8 7500 11000101. 24375 01000100.8 6875 11001011. 23750 01001010.8 6250 11001001. 23125 01001000.8 5625 11001111. 22500 01001110.8 5000 11001101. 21875 01001100.8 4375 11010011. 21250 01010010.8 3750 11010001. 20625 01010000.8 3125 table 7. voltage identifications (vid) for intel vr10 mode + 6.25 mv (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 output voltage vid4 vid3 vid2 vid1 vid0 vid5 vid6 output voltage
electrical specifications L6756D 18/36 table 8. gate output connections for phase # definition mode gate output connections g1 g2 g3 g4 2-phase to driver gnd to driver gnd 3-phase to driver to driver to driver gnd 4-phase to driver to driver to driver to driver
L6756D device description and operation 19/36 4 device description and operation L6756D is a programmable two-to-four phase pwm controller providing complete control logic and protections for a high performance step-down dc-dc voltage regulator optimized for advanced microprocessor power supply. th e device is a dual-edge asynchronous pwm controller featuring patented ltb technology ? : through a load transient detector, it turns on simultaneously all the phases allowing to minimi ze output voltage deviation so minimizing the system cost by providing the fast est response to a load transition. multi-phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current vrm modules. it allows distributing equally load and power between the phases using smaller, cheaper and most common external power mosfets and inductors. moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. phase interleaving causes in fact input rms current and output ripple voltage reduction and show an effective output switching frequency increase: the 200 khz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases. L6756D permits easy system design by allowing current reading across inductor in fully differential mode. also a sense resistor in series to the inductor can be considered to improve reading precision. the current information read corrects the pwm output in order to equalize the average current carried by each phase. the controller includes multiple dacs, sele ctable through an apposite pin, allowing compatibility with intel vr10, vr 11 and vr11.1 processors spec ifications, also performing d-vid transitions accordingly. the device is vr11.1 compatible implementing the imon signal and managing the psi# signal to enhance the system performances at low current in low power-states. low-side-less start-up allows soft-start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. L6756D provides overvoltage protection to protect the load from dangerous over stress latching immediately by turning on the lower driver and driving high the fault pin. the device is available in a compact vfqfpn40 with 6x6 mm body package.
output voltage positioning L6756D 20/36 5 output voltage positioning output voltage positioning is performed by selecting the controller operation mode ( vr10, vr11 or vr11.1 ) and by programming the droop function and offset to the reference of both the sections (see figure 6 ). the controller reads the current delivered by monitoring the voltage drop across the inductors dcr. the current (i droop ) sourced from the droop pin, directly proportional to the read current, causes the output voltage to vary according to the external r fb resistor so implementing the desired load-line effect. a fixed current (i os ) is sunk through the vsen pins ca using the output vo ltage to be offset according to the resistance r os connected. L6756D allows to recover from gnd losses in order to regulate remotely the programmed voltage without any additional external components. in this way, the output voltage programmed is regulated compensating for board and socket losses. keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. both droop and offset function can be disabled. in case droop effect is not desired, the current information source from the droop pin may be used to implement a secondary load indicator as reported in section 5.3 . figure 6. voltage positioning 5.1 phase # programming L6756D implements a flexible 2 to 4 interleaved-phase converter. to program the desired number of phase, refer to ta bl e 8 . for the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioni ng: csx needs to be connected to the regu- lated output voltage while csxn needs to be connected to csx with the same r g resistor used for the other phases. 2%&%2%.#% &" #/-0 63%. &"' 2 & # & 2 &" 4o6dd#/2% 2emote3ense ) $2//0 6$20 0rotection -onitor from$ !# 2 /3 !-v
L6756D output voltage positioning 21/36 5.2 current reading an d current sharing loop L6756D embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense re sistor placed in series to the inductor ele- ment. the fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. the trans-conductance ratio is issued by the external resistor r g placed outside the chip between csxn pin toward the reading points. the current sense circuit always tracks the current information, the pin csx is used as a reference keeping the csxn pin to this voltage. to correctly reproduce the inductor current an r-c filtering network must be introduced in parallel to the sensing ele- ment. the current that flows from the csxn pin is then given by the following equation (see figure 7 ): considering now to match the time constant between the inductor and the r-c filter applied (time constant mismatches caus e the introduction of poles into the current reading network causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance) it results: r g resistor is tipical designed in order to have an information current i infox in the range of 35 a at the oc threshold. the current read through the csx / csxn pairs is converted into a current i infox propor- tional to the current delivered by each phase and the information about the average current i avg = i infox / n is internally built into the device (n is the number of working phases). the error between the read current i infox and the reference i avg is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. figure 7. current reading connections i csx- dcr r g ------------- 1 s l dcr ? ? + 1src ?? + ------------------------------------- - i ? phasex ? = l r l ------ - rc i csxn r l rg ------- - i phasex ? = ? ? i infox == ,x #3x #3x. $#2 x 2 # 2 ' ) 0(!3%x ) #3x. ) ).&/x 6 /54 !-v
output voltage positioning L6756D 22/36 5.3 output voltage load-line definition L6756D is able to introduce a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current. figure 7 shows the current sense circuit used to implement the load-line. the current flowing across the inductor(s) is read through the r - c filter across csx and csxn pins. r g programs a transconductance gain and generates a current i csx proportional to the current of the phase x. the sum of the i csx current is then sourced by the vfb pin (i droop ). r fb gives the final gain to program the desired load-line slope ( figure 6 ). time constant matching between the inductor (l / dcr) and the current reading filter (rc) is required to implement a real equivalent output impedance of the system so avoiding over and/or under shoot of the output voltage as a consequence of a load transient. the output characteristic vs. load current is then given by (offset disabled): where r ll is the resulting load-line resistance implemented by the controller. the whole power supply can be then represented by a ?real? voltage generator with an equivalent output resistance r ll and a voltage value of vid. r fb resistor can be then designed according to the r ll specifications as follow: note: load-line (droop) implementation is optional, in case it is not desired, the resulting current information available on vdrp may be employed for other purposes, such as an additional load indicator (li2). in this case, simply connect a resistor r li2 to sgnd: the resulting voltage drop across r li2 will be proportional to the de livered current according to the following relationship: in case no additional information about the delivered current is requested, the vdrp pin can be shorted to sgnd. 5.4 output voltage offset the current (i os ) sunk from the vsen pin allows programming a positive offset (v os ) for the output voltage by connecting a resistor r os to v out in series to the fb loop. the sunk cur- rent generates a voltage drop according to the connected r os . output voltage is then pro- grammed as follow: caution: offset resistor impacts the voltage positioning! it need to be considered in series to r fb . note: offset implementation is opt ional: in case it is not desi red, simply consider using r os = 0 . v out vid r fb i droop ? ? vid r fb dcr r g ------------- i out ?? ? vid r ll i out ? ? == = r fb r ll r g dcr ------------- ? = v li2 r li2 dcr r g ------------- i out ?? = v core vid r fb r os + () i droop r os i os ? + ? ? =
L6756D output voltage positioning 23/36 5.5 dynamic vid transitions L6756D manages dynamic vid transitions that allow the output voltage to modify during normal device operation for cpu power management purposes. ov and uv signals are properly masked during every dvid transition and they are re-activated with a 16 clock cycle delay to prevent from false triggering. when changing dynamically the regulated voltage (dvid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i dvid needs to be delivered (especially when increasing the output regulated voltage) and it must be con- sidered when setting the over current threshold of both the sections. this current results: where dv out / dt vid depends on the operative mode (typically externally driven). dynamic vid transition is managed by checking for vid code modifications (see figure 8 ) on the rising edge of an internal additional dvid-clock and waiting for a confirmation on the following falling edge. once the new code is stable, on the next rising edge, the reference starts stepping up or down in lsb increments every two dvid-clock cycle until the new vid code is reached. dvid-clock frequency (f dvid ) is 1 mhz (typ). caution: overcoming the oc threshold during the dvid causes the device latch and disable. caution: if the new vid code is more than 1 lsb differ ent from the previous, the device will execute the transition stepping the reference with the dvid-clock frequency f dvid until the new code has reached. the output voltage rate of change will be of [lsb]mv * f dvid ! figure 8. dvid transitions i dvid c out dv out dt vid ------------------ ? = 4 $6)$ x3tep6)$4ransition t t t 6)$3ampled 6)$3ampled 6)$3ampled 2ef-oved 2ef-oved 2ef-oved 2ef-oved 6)$3table 6)$;= )nt2eference 6 out 4 sw 6)$3ampled 6)$3ampled 2ef-oved 2ef-oved 2ef-oved 6)$3ampled 6)$3ampled x3tep6)$4ransition 4 6)$ 6)$3ampled 6)$3ampled 6)$3ampled 6)$3ampled 6)$3ampled 6)$3table 6)$3table 6)$3table 2ef-o ved 6)$3ampled 6)$3ampled 6)$3table 6)$3ampled 6)$3ampled 6)$3ampled t 6)$#loc k 6out3lope#ontrolledbyinternal $6)$ #lock/scillator 6out3lope#ontrolledbyexternal drivingcircuit4 6)$ !-v
output voltage positioning L6756D 24/36 5.6 soft-start L6756D implements a soft-start to smoothly ch arge the output filter avoiding high in-rush currents to be required to the input power supply. during this phase, the device increases the reference from zero up to the programmed reference in closed loop regulation. soft-start is implemented only when all the power supplies are above their own turn-on thresholds and the en pin is set free. at the end of the digital soft-start, vr_rdy signal is set free. soft-start phase is initiated with a t1 = 2 ms (min) delay. after that, the reference ramps up to v boot = 1.081 v in t2 according to the r ss settings and waits for t3 = 200 sec (typ) during which the device reads the vid lines . output voltage will th en ramps up to the programmed value in t4 with the same slope as before (see figure 9 ). ss sets the output voltage dv/dt during soft-start according to the resistor r ss connected to sgnd. soft-start time t ss will proportionally change wit h a gain of 18.52 [s / k ]. connect 27 k resistor to program t2 = 500 s. protections are active during soft-start, uvp is enabled after the reference reaches 0.5 v while ovp is always active with a fixed 1.24 v threshold before v boot and with the threshold coming from the vid after v boot (see red-dashed line in figure 9 ). note: if during t3 the programmed vid selects an output voltage lower than v boot , the output voltage will ramp to the progra mmed voltage starting from v boot . note: the vid code is checked at the end of t3. in case the device is enabled over an off code, the output voltage will rise up to v boot and then device will latch. vid lines does not show any pull-up and/or pull-down before t3. figure 9. soft-start timings %. 62?2$9 6 /54 t t t 4 4 4 4 4 33 /604h !-v
L6756D output voltage positioning 25/36 5.6.1 lsless start-up in order to avoid any kind of negative undershoot on the load side during start-up, L6756D performs a special sequence in enabling the drivers for both sections: during the soft-start phase, the ls driver results to be disabled (ls = off - gx set to hiz and drvon = 0) until the first pwm pulse. after the first pwm pulse, gx outputs switches between logic ?0? and logic ?1? and drvon is set to logic ?1?. this particular sequence avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. low-side mosfet turn-on is masked only from the control loop point of view: protections are still allowed to turn-on the low-side mo sfet in case of overvoltage if needed. figure 10. lsless start-up: enabled (left) and disabled (right) !-v
output voltage monitoring and protections L6756D 26/36 6 output voltage monitoring and protections L6756D monitors through pin vsen the regu lated voltage in order to manage ov and uv. the device shows different thresholds when in different operative conditions but the behavior in response to a protection event is still the same as described below. 6.1 overvoltage once vcc crosses the turn-on threshold and the device is enabled (en = 1), L6756D provides an overvoltage prot ection by sensing the regulat ed voltage through vsen: when it overcomes the programmed vid +200 mv (max) the controller: ? permanently sets gx to zero keeping drvon high in order to keep all the low-side mosfets on to protect the load. ? drives the osc/ flt pin high. ? power supply or en pin cycling is required to restart operations. 6.2 feedback disconnection this feature acts in order to stop the device from regulating dangerous voltages in case the remote sense connections are left floating. the protection is available for both the positive and negative sense. according to what reported in figure 11 , the protection works as follow: ? positive sense consider to monitor t he core output volta ge through both vsen and csxn. as soon as csxn is more th an 650 mv higher th an vsen, the device latches with all gx set to hiz and drvon set to zero. flt pin is driven high. in any case, the 50 a pull-down current on the vsen (offset) forces the device to detect the fault condition. ? negative sense consider to monitor the internal opamp used to recover the sgnd losses by comparing its output and the internal reference generated by the dac. as soon as the difference between the output and the input of this opamp is higher than 500mv, the device latches with all gx set to hiz and drvon set to zero. flt pin is driven high. ? to recover from a latch condition, cycle vcc or en. figure 11. fb disconnection protection 2%&%2%.#% &" #/-0 63%. &"' 2 & # & 2 &" 4o6dd#/2% 2emote3ense from$!# m6 &"'$)3#/..%#4%$ #3x 63%. $)3#/..%#4%$ p ! m6 !-v
L6756D output voltage monitoring and protections 27/36 6.3 vr_rdy it is an open-drain signal set free after the soft-start sequence has finished. 6.4 over current the over current threshold has to be programmed to a safe value, in order to be sure that the system doesn't enter oc du ring normal operation. this value must take into consideration also the extra current needed during the dvid transition (i dvid ) and the process spread and temperature variations of the sensing elements (inductor dcr). moreover, since also the internal threshol d spreads, the design has to consider the minimum/maximum value of the thresholds. L6756D monitors the average current and allows to set the oc threshold by programming r ilim . ilim pin allows to define a maximum average output current for the system (i max ). a copy of the droop current is sourced from the ilim pin. by connecting a resistor r ilim to sgnd, a load indicator with 1.7 v (v oc ) end-of-scale can be implemented. this means that when the voltage present at the ilim pin crosses 1.7 v, the device detects an oc and immediately latches with all the mosfets off (hiz). typical design flow is the following: ? define the maximum average output current (i max ) according to system requirements ?design r g resistor in order to have i infox = 35 a when i out is about 10 % higher than the i max current. it results: where n is the number of phases and dcr th e dc resistance of the inductors. r g design must be typically performed in worst-case conditions. ?design r ilim in order to have the ilim pin to v oc at the desired i max current. it results: where i max is the oc threshold desired. ? adjust the defined values according to bench-test of the application. note: oc intervention can be delayed by adding a capacitor in parallel to the above defined r ilim . r g 1.1 i max ? () dcr ? ni ? octh ------------------------------------------------ = r ilim v ocavg r g ? i max dcr ? ---------------------------------- - 1.7v r g ? i max dcr ? ------------------------------ ==
low power-state management and psi# L6756D 28/36 7 low power-state management and psi# psi# is an active-low input that can be set by the cpu to allow the regulator to enter power- saving mode to maximize the system efficiency when in light-load conditions. the controller constantly monitors the psi_a pin to define the psi strategy, that is the action performed by the controller when psi# is asserted. according to ta b l e 9 , by programming different voltages on psi_a, it is possible to configure the device to work at one or two phases while psi# is asserted. the device can also be conf igured to take no action so phase number will not change after psi# assertion. in case the phase number is ch anged, the device will disable on e or more phases by setting in hiz the relative pwm and re-configuring the internal phase-shift to maintain the interleaving. furthermore, the in ternal current-sharing will be ad justed to cons ider the phase number reduction. endr v will remain asserted. when psi# is de-asserted, the device will return to the orig inal configuration. start-up is performed with all the configured phases enabled. in case of dvid transitions, the device will use all the phases available to pe rform the transition co ming back to the psi reduced number of phases after the transition has. psi strategy is continuously monitored across psi_a pin. caution: when psi_a is set for working at 2phases wh en psi# is asserted, the ic will work as if configured for 2phases so enabling only phase1 and phase3. table 9. psi strategy figure 12. system efficiency enhancement by psi# psi_a psi strategy psi#/vr10 gnd / open no strategy. ic will work in vr11 mode vr10 100 k to vref phase number set to 2 while psi# is asserted (only phase1 and phase3 are active). psi# to vref phase number set to 1 while psi# is asserted (only phase1 is active). !-v
L6756D main oscillator 29/36 8 main oscillator the internal oscillator generates the tria ngular waveform for the pwm charging and discharging with a constant current an internal capacitor. the switching frequency for each channel, f sw , is internally fixed at 200 khz: the resulting switching frequency at the load side results in being multiplied by n (number of configured phases). the current delivered to the oscillator may be varied using an external resistor (r osc ) typically connected between the osc pin and sgnd. since the osc pin is fixed at 1.24 v, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 10 khz/ a (see figure 13 ). connecting r osc to sgnd the frequency is increased (current is sunk from the pin), according to the following relationships: figure 13. r osc vs. switching frequency per phase f sw 200khz 1.240v r osc k () ---------------------------- 10 khz a ---------- - ? + = !-v
system control loop compensation L6756D 30/36 9 system control loop compensation the control system can be modeled with an e quivalent single-phase converter which only difference is the equivalent inductor l/n (where each phase has an l inductor and n is the number of the configured phases). see figure 14 . figure 14. equivalent control loop the control loop gain results (obtained opening the loop after the comp pin): where: r ll is the equivalent output resistance dete rmined by the droop function (voltage positioning); z p (s) is the impedance resulting by the parallel of the output capacitor (and its esr) and the applied load r o ; z f (s) is the compensation network impedance; z l (s) is the equivalent inductor impedance; a(s) is the erro r amplifier gain; is the pwm transfer function. the control loop gain is designed in order to obtain a high dc gain to minimize static error and to cross the 0 db axes with a constant -20 db/dec slope with the desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. 2ef &" #/-0 63%. &"' 2 & # & 2 &" 6$20 07- ,. %32 # / 2 / d6 #/-0 6 /54 : & s : &" s ) $2//0 6)$ 6 #/-0 !-v g loop s () pwm z f s () r ll z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------- ? = pwm 6 10 ------ v in v osc ------------------ - ? =
L6756D system control loop compensation 31/36 figure 15. control loop bode diagram and fine tuning to obtain the desired shape an r f -c f series network is considered for the z f (s) implementation. a zero at f =1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance assures a simple -20 db/dec shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results to be at frequency lower than the above reported zero. compensation network can be simply designed placing f = lc and imposing the cross- over frequency t as desired obtaining (always considering that t might be not higher than 1/10 th of the switching frequency f sw ): 9.1 compensation network guidelines the compensation network design assures to having system response according to the cross-over frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system as follow (see figure 15 ): ? increase r f to increase the system bandwidth accordingly; ? decrease r f to decrease the system bandwidth accordingly; ? increase c f to move f to low frequencies increasing as a consequence the system phase margin. having the fastest compensation network gives not the confidence to satisfy the requirements of the load: th e inductor still limits the maxi mum di/dt that the system can afford. in fact, when a load transient is applied, the best that the controller can do is to ?saturate? the duty cycle to its maximum (d max ) or minimum (0) value. the output voltage dv/dt is then limited by the inductor charge / discharge time and by the output capacitance. in particular, the most limiting transition corresponds to the load-removal since the inductor results being discharged only by v out (while it is charged by v in -v out during a load appliance). d" w : & s ' ,//0 s + w ,# w & w %32 w 4 2 & ;d"= d" w : & s ' ,//0 s + w ,# w & w %32 w 4 2 & ;d"= 2 & # & !-v r f r fb v osc ? v in --------------------------------- - 10 6 ------ t l nr ll esr + () ? ------------------------------------------ - ??? = c f c o l ? r f ------------------- - =
system control loop compensation L6756D 32/36 note: the introduction of a capacitor (c i ) in parallel to r fb significantly speeds-up the transient response by coupling the output voltage dv/dt on the fb pin so using the error amplifier as a comparator. the comp pin will suddenly reacts and, also thanks to the ltb technology ? control scheme, all the phases can be turned on together to immediately give to the output the required energy. typical design considers to start from values in the range of 100pf validating the effect by bench testing. additional series resistor (r i ) can also be used. 9.2 ltb technology ? lt b te c h n o l o gy ? further enhances the performances of dual-edge asynchronous systems by reducing the system latencies and immediatel y turning on all the phases to provide the correct amount of energy to the load. by properly deigning the ltb network as well as the ltb gain, the undershoot and the ring-back can be minimized also optimizing the output capacitors count. lt b te c h n o l o gy ? monitors the output voltage through a dedicated pin detecting load- transients with selected dv/dt, it cancels the interleaved phase-shift, turning-on simultaneously all phases. it then implements a parallel, independent loop that reacts to load-transients bypassing e/a latencies. lt b te c h n o l o gy ? control loop is reported in figure 16 . figure 16. ltb technology ? control loop the ltb detector is able to detect output load transients by coupling the output voltage through an r lt b - c lt b network. after detecting a load transient, the ltb ramp is reset and then compared with the comp pin level. the resulting duty-cycle pr ogrammed is then or- ed with the pwmx signal of each phase by-pas sing the main control loop. all the phases will then be turned-on together and the ea latencies results bypassed as well. 2ef &" #/-0 $)&&/54 &"' 2 & # & 2 &" 6$20 07- ,. %32 # / 2 / d6 #/-0 6 /54 : & s : &" s 6)$ 6 #/-0 # ( # &" ,4 " ) $2//0 -onitor 2 ,4 " # ,4 " 07-?"//34 ,4"2amp ,4" ,4$etect ,4$etect !-v
L6756D system control loop compensation 33/36 sensitivity of the load transient detector and the gain of the ltb ramp can be programmed in order to control precisely both the undershoot and the ring-back. detector design. r lt b - c lt b is design according to the output voltage deviation dv out which is desired the controller to be sensitive as follow: gain design. through the ltbgain pin it is possible to modify the slope of the ltb ramp in order to modulate the entity of the ltb response once the lt has been detected. in fact, the response depends on the board design and its parasites requiring different actions from the controller. leaving the ltbgain pin floating, the maximum pulse-width is programmed. the slope of the ltb ramp will be equal to 1/2 of the osc ramp slope. connecting r ltbgain to gnd, the ltb ramp slope can be modified as follow: where i ltbgain is the current sunk from ltbgain pin and i osc is the osc current (20 a plus the current coming from the osc pin). lt b te c h n o l o gy ? design tips. ? descries r lt b to increase the system sensitivity making the system sensitive to smaller dv out . ? increase c lt b to increase the syste m sensitivity making the system sensitive to higher dv/dt. ? increase r ltbgain to increase the width of the ltb pulse. r ltb dv o ut 25 a ------------------ = c ltb 1 2 nr ltb f sw ?? --------------------------------------------- - = ltbramp slope osc slope 1 i ltbgain i osc ----------------------- - + ?? ?? ? =
mechanical data and package dimensions L6756D 34/36 10 mechanical data and package dimensions in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 17. mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 0.800 0.900 1.000 0.031 0.035 0.039 a1 0.020 0.050 0.0008 0.0019 b 0.180 0.250 0.300 0.007 0.009 0.012 d 5.900 6.000 6.100 0.232 0.236 0.240 d2 3.950 4.100 4.200 0.155 0.161 0.165 e 5.900 6.000 6.100 0.232 0.236 0.240 e2 3.950 4.100 4.200 0.155 0.161 0.165 e 0.500 0.020 l 0.300 0.400 0.500 0.012 0.015 0.018 ddd 0.080 0.003 vfqfpn-40 (6x6x1.0mm) v ery f ine q uad f lat p ackage n o lead ddd
L6756D revision history 35/36 11 revision history table 10. document revision history date revision changes 01-oct-2008 1 initial release
L6756D 36/36 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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